1. Field of the Invention
The present invention relates to a semiconductor device, and an associated alignment apparatus and alignment method, and more particularly it relates to a semiconductor device having an alignment mark that occupies a reduced surface area, and an alignment apparatus suitable for this semiconductor device that shortens the alignment time.
2. Description of the Related Art
In an alignment apparatus, when alignment marks that are formed in different base layers are used to perform alignment, in the case for example in which the alignment marks in the lowermost layer are used to perform alignment on the upper layer, because light used in the alignment passes through an interlayer film, an error occurs, this resulting in a reduction of alignment accuracy.
In the case in which the alignment marks that are formed on the upper layer are used to achieve positioning, that is, alignment, between a mask and a wafer, because of the cumulative errors that are included in each mark formed in the various process steps, there is a problem with alignment error.
In general, the selection of the ideal alignment marks to use is done at each alignment separately during the alignment steps.
For this reason, because alignment upper layers is performed by detecting the alignment marks formed in each layer and comparing this data so as to select the best alignment mark, the processing of alignment took a great deal of time in the past.
In the past, alignment marks, as shown in FIG. 5, have a width in the scanning direction of (diffraction grating distance X).times.(diffraction grating number of lines), this being a width of 100 .mu.m or greater, and because alignment is performed with a plurality of base layers, the alignment marks, as denoted by 21 and 22 in FIG. 5, inevitably occupy a considerable amount of surface area, this presenting the problem of hindering the achievement of a high degree of integration in the semiconductor integrated circuit.
Known alignment apparatuses are such as described, for example, in Japanese Unexamined Patent Publication (KOKAI) No.63-237522, Japanese Examined Patent Publication (KOKOKU) No.1-20529, Japanese Examined Patent Publication (KOKOKU) No.2-63287, Japanese Unexamined Patent Publication (KOKAI) No.64-25413, but these alignment apparatuses do not solve the above-described problems.
Accordingly, it is an object of the present invention to provide a solution to the drawbacks in the prior art as noted above, and in particular to provide a novel semiconductor device that alignment marks having a reduction in the surface area occupied on the semiconductor chip.
Another object of the present invention is to provide a novel alignment apparatus and alignment method that reduce the amount of time required to perform alignment.